1. Field of the Invention
The invention generally relates to modules for semiconductor device chips and, more particularly, to such modules having two contiguous groups of internal wiring planes providing wiring channels running in different respective directions.
2. Description of the Prior Art
Various methods have been employed for routing interconnecting wires for chips mounted on ceramic substrates. Basically, the methods fall into two categories, i.e., the interconnecting lines run rectangularly (parallel to the sides of the module) or diagonally relative to the sides of the module. The optimum connecting path of minimum length is selected depending upon the location of the two chip terminals to be connected together relative to the existing rectangular or diagonal pathway. Vias are used to change wiring direction from north-south to east-west, for example.
The considerations involved in choosing rectangular or diagonal chip interconnecting pathways on a module are discussed in IBM.RTM. Technical Disclosure Bulletins of June 1981, page 730 "45% Wiring Layers For A Thin Film Module Package" by A. Deutsch and C. W. Ho, and September 1971, page 1316 "Use Of Relatively Diagonal And Rectangular Wiring Planes In Multilayer Packages" by E. C. Layden.
The former TDB points out the potential line length savings in using diagonal interconnecting lines to meet the demands of very large scale integration chip modules. Reducing the length of chip interconnections on a module not only reduces resistive losses but propagational delays as well. The cited September 1971 TDB teaches the use of a mixture of rectangular and diagonal wiring levels in a multilevel board, the two different routing directions being employed on alternate levels throughout the board. Shortest path connections from the chips to the selected rectangular or diagonal wiring level are made through interstitial vias which run transversely through the board into contact with the wiring pathways available on the opposite sides of the various board levels.
The January 1978 TDB, page 3092, shows a semiconductor package structure having a multilevel metallurgy system, each level comprising orthogonal wiring plane pairs. In order to minimize cross-sectional noise coupling, the adjacent wiring plane pairs (each of which are provided with rectangular wiring pathways) are disposed diagonally with respect to each other.
U.S. Pat. No. 4,298,770, issued on Nov. 3, 1981 to Nishihara et al. and entitled "Printed Board" discloses the application of rectangular and diagonal conduction pathways to printed circuit boards. The concepts are modified somewhat with respect to the other cited prior art, in that several different diagonal directions are proposed in order to increase wiring pattern selection flexibility over the case where only 45.degree. diagonal directions are made available to the module wiring designer.
Although the prior art wiring techniques address the general problem of wire routing on a given level to achieve reduced wiring path lengths between points which are desired to be interconnected, close attention has not been directed to the overall optimization of level wiring as well as via interconnection wiring along the third dimension, i.e., the depth dimension of the module.